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| HT46R46/ht46c46/ht46r47/ht46c47 cost-effective a/d type 8-bit mcu rev. 1.00 1 december 28, 2004 general description the HT46R46/ht46c46 and ht46r47/ht46c47 are 8-bit, high performance, risc architecture microcontroller devices specifically designed for a/d applications that interface directly to analog signals, such as those from sensors. the mask version ht46c46, ht46c47 are fully pin and functionally com- patible with the otp version HT46R46, ht46r47 de- vice. the advantages of low power consumption, i/o flexibil - ity, programmable frequency divider, timer functions, oscillator options, multi-channel a/d converter, pulse width modulation function, halt and wake-up func- tions, enhance the versatility of these devices to suit a wide range of a/d application possibilities such as sen- sor signal processing, motor driving, industrial control, consumer products, subsystem controllers, etc. features operating voltage: f sys =4mhz: 2.2v~5.5v f sys =8mhz: 3.3v~5.5v 13 bidirectional i/o lines (max.) 1 interrupt input shared with an i/o line 8-bit programmable timer/event counter with overflow interrupt and 7-stage prescaler on-chip crystal and rc oscillator watchdog timer 1024 14 program memory for HT46R46/ht46c46 2048 14 program memory for ht46r47/ht46c47 64 8 data memory ram supports pfd for sound generation halt function and wake-up feature reduce power consumption up to 0.5 s instruction cycle with 8mhz system clock at v dd =5v 4-level subroutine nesting for HT46R46/ht46c46 6-level subroutine nesting for ht46r47/ht46c47 4 channels 8-bit resolution a/d converter for HT46R46/ht46c46 4 channels 9-bit resolution a/d converter for ht46r47/ht46c47 1 channel 8-bit pwm output shared with an i/o line bit manipulation instruction 14-bit table read instruction 63 powerful instructions all instructions in one or two machine cycles low voltage reset function 18-pin dip/sop package
block diagram HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 2 december 28, 2004 ! " ! # $ % " ! ! % % " ! " & ' ( ! ) ! ! * + , - , . + ) / % " 0 ) / 1 + + 2 ( 0 3 1 1 4 , , 1 4 , - 5 4 6 ' pin assignment pin description pin name i/o options description pa0~pa2 pa3/pfd pa4/tmr pa5/int pa6, pa7 i/o pull-high wake-up pa3 or pfd bidirectional 8-bit input/output port. each bit can be configured as wake-up input by options. software instructions determine the cmos output or schmitt trigger input with or without pull-high resistor (determined by pull-high options: bit option). the pfd, tmr and int are pin-shared with pa3, pa4 and pa5, re - spectively. pb0/an0 pb1/an1 pb2/an2 pb3/an3 i/o pull-high bidirectional 4-bit input/output port. software instructions determine the cmos output, schmitt trigger input with or without pull-high resistor (deter - mined by pull-high options: bit option) or a/d input. once a pb line is selected as an a/d input (by using software control), the i/o function and pull-high resistor are disabled automatically. pd0/pwm i/o pull-high pd0 or pwm bidirectional i/o line. software instructions determine the cmos output, schmitt trigger input with or without a pull-high resistor (determined by pull-high options: bit option). the pwm output function is pin-shared with pd0 (dependent on pwm options). res i schmitt trigger reset input. active low. vdd positive power supply vss negative power supply, ground. osc1 osc2 i o crystal or rc osc1, osc2 are connected to an rc network or a crystal (determined by options) for the internal system clock. in the case of rc operation, osc2 is the output terminal for 1/4 system clock. absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 40 cto85 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil - ity. HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 3 december 28, 2004 5 6 1 + , - 1 , , 1 1 7 6 5 , 1 , 5 6 7 8 d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage f sys =4mhz 2.2 5.5 v f sys =8mhz 3.3 5.5 v i dd1 operating current (crystal osc) 3v no load, f sys =4mhz adc disable 0.6 1.5 ma 5v 24ma i dd2 operating current (rc osc) 3v no load, f sys =4mhz adc disable 0.8 1.5 ma 5v 2.5 4 ma i dd3 operating current (crystal osc, rc osc) 5v no load, f sys =8mhz adc disable 48ma i stb1 standby current (wdt enabled) 3v no load, system halt 5 a 5v 10 a i stb2 standby current (wdt disabled) 3v no load, system halt 1 a 5v 2 a v il1 input low voltage for i/o ports, tmr and int 0 0.3v dd v v ih1 input high voltage for i/o ports, tmr and int 0.7v dd v dd v v il2 input low voltage (res ) 0 0.4v dd v v ih2 input high voltage (res ) 0.9v dd v dd v v lvr low voltage reset 2.7 3 3.3 v i ol i/o port sink current 3v v ol =0.1v dd 48 ma 5v v ol =0.1v dd 10 20 ma i oh i/o port source current 3v v oh =0.9v dd 2 4 ma 5v v oh =0.9v dd 5 10 ma r ph pull-high resistance 3v 20 60 100 k 5v 10 30 50 k v ad a/d input voltage 0 v dd v e ad a/d conversion error 0.5 1 lsb i adc additional power consumption if a/d converter is used 3v 0.5 1 ma 5v 1.5 3 ma HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 4 december 28, 2004 a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys system clock 2.2v~5.5v 400 4000 khz 3.3v~5.5v 400 8000 khz f timer timer i/p frequency (tmr) 2.2v~5.5v 0 4000 khz 3.3v~5.5v 0 8000 khz t wdtosc watchdog oscillator period 3v 45 90 180 s 5v 32 65 130 s t wdt1 watchdog time-out period (rc) 2 15 2 16 t wdtosc t wdt2 watchdog time-out period (system clock) 2 17 2 18 t sys t res external reset low pulse width 1 s t sst system start-up timer period wake-up from halt 1024 *t sys t int interrupt pulse width 1 s t ad1 a/d clock period for HT46R46/ht46c46 0.5 s t ad2 a/d clock period for ht46r47/ht46c47 1 s t adc1 a/d conversion time for HT46R46/ht46c46 64 t ad1 t adc2 a/d conversion time for ht46r47/ht46c47 76 t ad2 t adcs1 a/d sampling time for HT46R46/ht46c46 32 t ad1 t adcs2 a/d sampling time for ht46r47/ht46c47 32 t ad2 note: *t sys =1/f sys HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 5 december 28, 2004 HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 6 december 28, 2004 functional description execution flow the system clock for the microcontroller is derived from either a crystal or an rc oscillator. the system clock is internally divided into four non-overlapping clocks. one instruction cycle consists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while de - coding and execution takes the next instruction cycle. however, the pipelining scheme causes each instruc - tion to effectively execute in a cycle. if an instruction changes the program counter, two cycles are required to complete the instruction. program counter pc the program counter (pc) controls the sequence in which the instructions stored in program rom are exe - cuted and its contents specify full range of program memory. after accessing a program memory word to fetch an in - struction code, the contents of the program counter are incremented by one. the program counter then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip ex - ecution, loading pcl register, subroutine call, initial re - set, internal interrupt, external interrupt or return from subroutine, the pc manipulates the program transfer by loading the address corresponding to each instruction. the conditional skip is activated by instructions. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. otherwise proceed with the next instruction. the lower byte of the program counter (pcl) is a read - able and writeable register (06h). moving data into the pcl performs a short jump. the destination will be within 256 locations. when a control transfer takes place, an additional dummy cycle is required. , , , - " ( 9 : ; " 9 2 : - " ( 9 < : ; " 9 : - " ( 9 < : ; " 9 < : < < $ % 0 " = 9 0 $ : execution flow mode program counter *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 00000000000 external interrupt 00000000100 timer/event counter overflow 00000001000 a/d converter interrupt 00000001100 skip program counter+2 loading pcl *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *10~*0: program counter bits s10~s0: stack register bits #10~#0: instruction code bits @7~@0: pcl bits for the ht46r47/ht46c47, the program counter is 11 bits wide, i.e. from *10~*0. for the HT46R46/ht46c46, the program counter is 10 bits wide, the *10 the column in the table is not applicable. HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 7 december 28, 2004 program memory rom the program memory is used to store the program in - structions which are to be executed. it also contains data, table, and interrupt entries, and is organized into 1k 14 bits, addressed by the program counter and table pointer. certain locations in the program memory are reserved for special usage: location 000h this area is reserved for program initialization. after chip reset, the program always begins execution at lo - cation 000h. location 004h this area is reserved for the external interrupt service program. if the int input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004h. location 008h this area is reserved for the timer/event counter inter - rupt service program. if a timer interrupt results from a timer/event counter overflow, and if the interrupt is en - abled and the stack is not full, the program begins exe - cution at location 008h. location 00ch this area is reserved for the a/d converter interrupt service program. if an a/d converter interrupt results from an end of a/d conversion, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00ch. table location any location in the rom space can be used as look-up tables. the instructions tabrdc [m] (the current page, 1 page=256 words) and tabrdl [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to tblh (08h). only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of tblh, and the remaining 2 bits are read as 0 . the table higher-order byte register (tblh) is read only. the table pointer (tblp) is a read/write reg - ister (07h), which indicates the table location. before accessing the table, the location must be placed in tblp. the tblh is read only and cannot be restored. if the main routine and the isr (interrupt service rou - tine) both employ the table read instruction, the con - tents of the tblh in the main routine are likely to be changed by the table read instruction used in the isr. > ! % 1 1 ? - - ? $ 3 ! " ! ! 0 ! @ ! ; 0 > ! ! 3 > ! ' = 2 > 0 9 5 a & % : ' = 2 > 0 9 5 a & % : b % ) 1 , 1 1 1 ? 1 1 ? 1 1 7 ? 3 > ! 1 1 ? , - - ? , 1 1 ? program memory for the HT46R46/ht46c46 instruction table location *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] p10 p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 table location note: *10~*0: table location bits p10~p8: current program counter bits @7~@0: table pointer bits for the ht46r47/ht46c47, the table address location is 11 bits, i.e. from *10~*0. for the HT46R46/ht46c46, the table address location is 10 bits, i.e. from *9~*0. > ! % 1 1 ? - - ? $ 3 ! " ! ! 0 ! @ ! ; 0 > ! ! 3 > ! ' = 2 > 0 9 5 a & % : ' = 2 > 0 9 5 a & % : b % ) 1 6 1 1 1 ? 1 1 ? 1 1 7 ? 3 > ! 1 1 ? 6 - - ? 6 1 1 ? program memory for the ht46r47/ht46c47 HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 8 december 28, 2004 errors can occur. in other words, using the table read instruction in the main routine and the isr simulta - neously should be avoided. however, if the table read instruction has to be applied in both the main routine and the isr, the interrupt is supposed to be disabled prior to the table read instruction. it will not be enabled until the tblh has been backed up. all table related instructions require two cycles to complete the opera - tion. these areas may function as normal program memory depending upon the requirements. stack register stack this is a special part of the memory which is used to save the contents of the program counter only. the stack is organized into 4 levels for the HT46R46/ ht46c46 or 6 levels for the ht46r47/ht46c47 and are neither part of the data nor part of the program space, and is neither readable nor writeable. the acti - vated level is indexed by the stack pointer (sp) and is neither readable nor writeable. at a subroutine call or in - terrupt acknowledgment, the contents of the program counter are pushed onto the stack. at the end of a sub - routine or an interrupt routine, signaled by a return in - struction (ret or reti), the program counter is restored to its previous value from the stack. after a chip reset, the sp will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. when the stack pointer is decremented (by ret or reti), the interrupt will be serviced. this feature prevents stack overflow al- lowing the programmer to use the structure more easily. in a similar case, if the stack is full and a call is sub- sequently executed, stack overflow occurs and the first entry will be lost (only the most recent 4 (ht46r47/ht46c46) or 6 (ht46r47/ht46c47) return addresses are stored). data memory ram the data memory is designed with 84 8 bits (HT46R46/ht46c46) or 85 8 bits (ht46r47/ht46c47). the data memory is divided into two functional groups: special function registers and general purpose data memory (64 8). most are read/write, but some are read only. the special function registers include the indirect ad - dressing register (00h), timer/event counter (tmr;0dh), timer/event counter control register (tmrc;0eh), program counter lower-order byte regis - ter (pcl;06h), memory pointer register (mp;01h), ac - cumulator (acc;05h), table pointer (tblp;07h), table higher-order byte register (tblh;08h), status register (status;0ah), interrupt control register (intc;0bh), pwm data register (pwm;1ah), the a/d result register (adr;21h) for the HT46R46/ht46c46, the a/d result lower-order byte register (adrl;20h) for the ht46r47/ht46c47, the a/d result higher-order byte register (adrh;21h) for the ht46r47/ht46c47, the a/d control register (adcr;22h), the a/d clock setting register (acsr;23h), i/o registers (pa;12h, pb;14h, pd;18h) and i/o control registers (pac;13h, pbc;15h, pdc;19h). the remaining space before the 40h is reserved for future expanded usage and reading these locations will get 00h . the general purpose data memory, addressed from 40h to 7fh, is used for data and control information under instruction com - mands. all of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations di - rectly. except for some dedicated bits, each bit in the data memory can be set and reset by set [m].i and clr [m].i . they are also indirectly accessible through memory pointer register (mp;01h). " ! 0 % / 1 1 ? 1 ? 1 ? 1 , ? 1 ? 1 ? 1 5 ? 1 6 ? 1 7 ? 1 8 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 - ? 1 ? ? ? , ? ? ? 5 ? 6 ? 7 ? 8 ? ? ? ? ? ? - ? & ! " & & % % ! ! % ' ' ' ? + b % & & % c 1 1 c , - ? ? 1 ? ? ? , ? * 0 % / 9 5 $ % : 6 - ? 1 ? ram mapping for the HT46R46/ht46c46 HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 9 december 28, 2004 indirect addressing register location 00h is an indirect addressing register that is not physically implemented. any read/write operation of [00h] accesses data memory pointed to by mp (01h). reading location 00h itself indirectly will return the re - sult 00h. writing indirectly results in no operation. the memory pointer register mp (01h) is a 7-bit register. the bit 7 of mp is undefined and reading will return the result 1 . any writing operation to mp will only transfer the lower 7-bit data to mp. accumulator the accumulator is closely related to alu operations. it is also mapped to location 05h of the data memory and can carry out immediate data operations. the data movement between two data memory locations must pass through the accumulator. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic opera - tions. the alu provides the following functions: arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz ....) the alu not only saves the results of a data operation but also changes the status register. status register status this 8-bit register (0ah) contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). it also records the status information and controls the operation sequence. bit no. label function 0c c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation, otherwise c is cleared. c is also affected by a rotate through carry instruction. 1ac ac is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction, otherwise ac is cleared. 2 z z is set if the result of an arithmetic or logic operation is zero, otherwise z is cleared. 3ov ov is set if an operation results in a carry into the highest-order bit but not a carry out of the high - est-order bit, or vice versa, otherwise ov is cleared. 4 pdf pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by exe - cuting the halt instruction. 5to to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6, 7 unused bit, read as 0 status (0ah) register " ! 0 % / 1 1 ? 1 ? 1 ? 1 , ? 1 ? 1 ? 1 5 ? 1 6 ? 1 7 ? 1 8 ? 1 ? 1 ? 1 ? 1 ? 1 ? 1 - ? 1 ? ? ? , ? ? ? 5 ? 6 ? 7 ? 8 ? ? ? ? ? ? - ? & ! " & & % % ! ! % ' ' ' ? + ' ? b % & & % c 1 1 c , - ? ? 1 ? ? ? , ? * 0 % / 9 5 $ % : 6 - ? 1 ? ram mapping for the ht46r47/ht46c47 HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 10 december 28, 2004 with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addi - tion operations related to the status register may give different results from those intended. the to flag can be affected only by system power-up, a wdt time-out or executing the clr wdt or halt in - struction. the pdf flag can be affected only by exe - cuting the halt or clr wdt instruction or a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations. in addition, on entering the interrupt sequence or exe - cuting the subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status are important and if the subroutine can cor - rupt the status register, precautions must be taken to save it properly. interrupt the device provides an external interrupt, internal timer/event counter interrupt and a/d converter inter - rupts. the interrupt control register (intc;0bh) con - tains the interrupt control bits to set the enable or disable and the interrupt request flags. once an interrupt subroutine is serviced, all the other in- terrupts will be blocked (by clearing the emi bit). this scheme may prevent any further interrupt nesting. other interrupt requests may happen during this interval but only the interrupt request flag is recorded. if a certain in- terrupt requires servicing within the service routine, the emi bit and the corresponding bit of intc may be set to allow interrupt nesting. if the stack is full, the interrupt re- quest will not be acknowledged, even if the related inter - rupt is enabled, until the sp is decremented. if immediate service is desired, the stack must be prevented from be - coming full. all these kinds of interrupts have a wake-up capability. as an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the pro - gram memory. only the program counter is pushed onto the stack. if the contents of the register or status register (status) are altered by the interrupt service program which corrupts the desired control sequence, the con - tents should be saved in advance. external interrupts are triggered by a high to low transi - tion of int and the related interrupt request flag (eif; bit 4 of intc) will be set. when the interrupt is enabled, the stack is not full and the external interrupt is active, a sub - routine call to location 04h will occur. the interrupt re - quest flag (eif) and emi bits will be cleared to disable other interrupts. the internal timer/event counter interrupt is initialized by setting the timer/event counter interrupt request flag (tf;bit 5 of intc), caused by a timer overflow. when the interrupt is enabled, the stack is not full and the tf bit is set, a subroutine call to location 08h will occur. the re - lated interrupt request flag (tf) will be reset and the emi bit cleared to disable further interrupts. the a/d converter interrupt is initialized by setting the a/d converter request flag (adf; bit 6 of intc), caused by an end of a/d conversion. when the interrupt is en - abled, the stack is not full and the adf is set, a subrou - tine call to location 0ch will occur. the related interrupt request flag (adf) will be reset and the emi bit cleared to disable further interrupts. during the execution of an interrupt subroutine, other in- terrupt acknowledgments are held until the reti in- struction is executed or the emi bit and the related interrupt control bit are set to 1 (of course, if the stack is not full). to return from the interrupt subroutine, ret or reti may be invoked. reti will set the emi bit to enable an interrupt service, but ret will not. interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in the case of simultaneous requests the following table shows the priority that is applied. these can be masked by resetting the emi bit. bit no. label function 0 emi controls the master (global) interrupt (1=enabled; 0=disabled) 1 eei controls the external interrupt (1=enabled; 0=disabled) 2 eti controls the timer/event counter interrupt (1=enabled; 0=disabled) 3 eadi controls the a/d converter interrupt (1=enabled; 0=disabled) 4 eif external interrupt request flag (1=active; 0=inactive) 5 tf internal timer/event counter request flag (1=active; 0=inactive) 6 adf a/d converter request flag (1=active; 0=inactive) 7 unused bit, read as 0 intc (0bh) register HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 11 december 28, 2004 interrupt source priority vector external interrupt 1 04h timer/event counter overflow 2 08h a/d converter interrupt 3 0ch the timer/event counter interrupt request flag (tf), ex - ternal interrupt request flag (eif), a/d converter request flag (adf), enable timer/event counter bit (eti), enable external interrupt bit (eei), enable a/d converter inter - rupt bit (eadi) and enable master interrupt bit (emi) constitute an interrupt control register (intc) which is located at 0bh in the data memory. emi, eei, eti, eadi are used to control the enabling/disabling of interrupts. these bits prevent the requested interrupt from being serviced. once the interrupt request flags (tf, eif, adf) are set, they will remain in the intc register until the in - terrupts are serviced or cleared by a software instruc - tion. it is recommended that a program does not use the call subroutine within the interrupt subroutine. in - terrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and enabling the interrupt is not well con trolled, the original control sequence will be dam - aged once the call operates in the interrupt subrou- tine. oscillator configuration there are two oscillator circuits in the microcontroller. both are designed for system clocks, namely the rc os - cillator and the crystal oscillator, which are determined by the options. no matter what oscillator type is se - lected, the signal provides the system clock. the halt mode stops the system oscillator and ignores an exter - nal signal to conserve power. if an rc oscillator is used, an external resistor between osc1 and vss is required and the resistance must range from 30k to 750k . the system clock, divided by 4, is available on osc2, which can be used to syn - chronize external logic. the rc oscillator provides the most cost effective solution. however, the frequency of oscillation may vary with vdd, temperatures and the chip itself due to process variations. it is, therefore, not suitable for timing sensitive operations where an accu - rate oscillator frequency is desired. if the crystal oscillator is used, a crystal across osc1 and osc2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. instead of a crystal, a resona - tor can also be connected between osc1 and osc2 to get a frequency reference, but two external capacitors in osc1 and osc2 are required (if the oscillating fre - quency is less than 1mhz). the wdt oscillator is a free running on-chip rc oscilla - tor, and no external components are required. even if the system enters the power down mode, the system clock is stopped, but the wdt oscillator still works with a period of approximately 65 s@5v. the wdt oscillator can be disabled by options to conserve power. watchdog timer wdt the clock source of wdt is implemented by a dedicated rc oscillator (wdt oscillator) or instruction clock (sys - tem clock divided by 4), decided by options. this timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. the watchdog timer can be disabled by an op - tion. if the watchdog timer is disabled, all the execu - tions related to the wdt result in no operation. once the internal oscillator (rc oscillator with a period of 65 s@5v normally) is selected, it is divided by 32768~65536 to get the time-out period of approxi- mately 2.1s~4.3s. this time-out period may vary with temperatures, vdd and process variations. if the wdt oscillator is disabled, the wdt clock may still come from the instruction clock and operate in the same manner except that in the halt state the wdt may stop count- ing and lose its protecting purpose. in this situation the logic can only be restarted by external logic. if the device operates in a noisy environment, using the on-chip rc oscillator (wdt osc) is strongly recom - mended, since the halt will stop the system clock. the wdt overflow under normal operation will initialize chip reset and set the status bit to . but in the halt mode, the overflow will initialize a warm reset , and only the program counter and sp are reset to zero. to clear the contents of wdt, three methods are adopted; external reset (a low level to res ), software instruction and a halt instruction. the software instruction include clr wdt and the other set clr wdt1 and clr wdt2 . of these two types of instruction, only one can be active depending on the options clr wdt times selection option .ifthe clr wdt is selected (i.e. clr wdt times equal one), any execution of the clr wdt instruction will clear the wdt. in the case that clr wdt1 and clr wdt2 are chosen (i.e. clr wdt times equal two), these two instructions must be executed to clear the wdt; otherwise, the wdt may re - set the chip as a result of time-out. $ % 0 % " ! 0 0 % " ! 0 0 ! ) / system oscillator HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 12 december 28, 2004 power down operation halt the halt mode is initialized by the halt instruction and results in the following... the system oscillator will be turned off but the wdt oscillator keeps running (if the wdt oscillator is se - lected). the contents of the on chip ram and registers remain unchanged. wdt will be cleared and recounted again (if the wdt clock is from the wdt oscillator). all of the i/o ports maintain their original status. the pdf flag is set and the to flag is cleared. the system can leave the halt mode by means of an external reset, an interrupt, an external falling edge sig - nal on port a or a wdt overflow. an external reset causes a device initialization and the wdt overflow per- forms a warm reset . after the to and pdf flags are examined, the reason for chip reset can be determined. the pdf flag is cleared by system power-up or execut- ing the clr wdt instruction and is set when execut- ing the halt instruction. the to flag is set if the wdt time-out occurs, and causes a wake-up that only resets the program counter and sp; the others keep their origi- nal status. the port a wake-up and interrupt methods can be con - sidered as a continuation of normal execution. each bit in port a can be independently selected to wake up the device by the options. awakening from an i/o port stim - ulus, the program will resume execution of the next in - struction. if it is awakening from an interrupt, two sequences may happen. if the related interrupt is dis - abled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. if the interrupt is enabled and the stack is not full, the regu - lar interrupt response takes place. if an interrupt request flag is set to 1 before entering the halt mode, the wake-up function of the related interrupt will be disabled. once a wake-up event occurs, it takes 1024 t sys (sys - tem clock period) to resume normal operation. in other words, a dummy period will be inserted after wake-up. if the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution will be delayed by one or more cycles. if the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. to minimize power consumption, all the i/o pins should be carefully managed before entering the halt status. reset there are three ways in which a reset can occur: res reset during normal operation res reset during halt wdt time-out reset during normal operation the wdt time-out during halt is different from other chip reset conditions, since it can perform a warm re - set that resets only the program counter and sp, leav- ing the other circuits in their original state. some regis- ters remain unchanged during other reset conditions. most registers are reset to the initial condition when the reset conditions are met. by examining the pdf and to flags, the program can distinguish between different chip resets . to pdf reset conditions 0 0 res reset during power-up u u res reset during normal operation 0 1 res wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note: u means unchanged $ % 0 " = 7 2 > ! 6 2 > ! ' + ! 0 " + + ! 2 ) 4 ) 5 ) watchdog timer HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 13 december 28, 2004 to guarantee that the system oscillator is started and stabilized, the sst (system start-up timer) provides an extra-delay of 1024 system clock pulses when the sys - tem reset (power-up, wdt time-out or res reset) or the system awakes from the halt state. when a system reset occurs, the sst delay is added during the reset period. any wake-up from halt will en - able the sst delay. an extra option load time delay is added during system reset (power-up, wdt time-out at normal mode or res reset). the functional unit chip reset status are shown below. program counter 000h interrupt disable wdt clear. after master reset, wdt begins counting timer/event counter off input/output ports input mode sp points to the top of the stack + % + ? ' 0 & % $ % % 1 2 > ! ! 0 reset configuration ! 2 ( ! % reset timing chart 1 1 = 1 = 1 d - e 1 d 1 - e reset circuit note: * make the length of the wiring, which is con - nected to the res pin as short as possible, to avoid noise interference. HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 14 december 28, 2004 the registers states are summarized in the following table. register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt times-out (halt)* mp -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu program counter 000h 000h 000h 000h 000h tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu intc -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu tmr xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmrc 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu pbc ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu pd ---- ---1 ---- ---1 ---- ---1 ---- ---1 ---- ---u pdc ---- ---1 ---- ---1 ---- ---1 ---- ---1 ---- ---u pwm xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adr (HT46R46/ht46c46) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrl (ht46r47/ht46c47) x--- ---- x--- ---- x--- ---- x--- ---- u--- ---- adrh (ht46r47/ht46c47) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adcr 0100 0000 0100 0000 0100 0000 0100 0000 uuuu uuuu acsr 1--- --00 1--- --00 1--- --00 1--- --00 u--- --uu note: * stands for warm reset u stands for unchanged x stands for unknown HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 15 december 28, 2004 bit no. label function 0 1 2 psc0 psc1 psc2 defines the prescaler stages, psc2, psc1, psc0= 000: f int =f sys 001: f int =f sys /2 010: f int =f sys /4 011: f int =f sys /8 100: f int =f sys /16 101: f int =f sys /32 110: f int =f sys /64 111: f int =f sys /128 3te defines the tmr active edge of the timer/event counter: in event counter mode (tm1,tm0)=(0,1): 1:count on falling edge; 0:count on rising edge in pulse width measurement mode (tm1,tm0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge 4 ton enable or disable the timer counting (0=disable; 1=enable) 5 unused bits, read as 0 6 7 tm0 tm1 defines the operating mode (tm1, tm0)= 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmrc (0eh) register timer/event counter a timer/event counter (tmr) is implemented in the microcontroller. the timer/event counter contains an 8-bit programmable count-up counter and the clock may come from an external source or the system clock. using external clock input allows the user to count exter - nal events, measure time internals or pulse widths, or generate an accurate time base. while using the inter - nal clock allows the user to generate an accurate time base. the timer/event counter can generate pfd signal by us - ing external or internal clock and pfd frequency is de - termine by the equation f int /[2 (256-n)]. there are 2 registers related to the timer/event counter; tmr ([0dh]), tmrc ([0eh]). two physical registers are mapped to tmr location; writing tmr makes the start - ing value be placed in the timer/event counter preload register and reading tmr retrieves the contents of the timer/event counter. the tmrc is a timer/event counter control register, which defines some options. the tm0, tm1 bits define the operating mode. the event count mode is used to count external events, which means the clock source comes from an external (tmr) pin. the timer mode functions as a normal timer with the clock source coming from the f int clock. the pulse width measurement mode can be used to count the high or low level duration of the external signal (tmr). the counting is based on the f int . in the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to ffh. once over - flow occurs, the counter is reloaded from the timer/event counter preload register and generates the interrupt re - quest flag (tf; bit 5 of intc) at the same time. in the pulse width measurement mode with the ton and te bits equal to one, once the tmr has received a transient from low to high (or high to low if the te bits is 0 ) it will start counting until the tmr returns to the orig - inal level and resets the ton. the measured result will remain in the timer/event counter even if the activated transient occurs again. in other words, only one cycle measurement can be done. until setting the ton, the cycle measurement will function again as long as it re - ceives further transient pulse. note that, in this operat - ing mode, the timer/event counter starts counting not according to the logic level but according to the transient edges. in the case of counter overflows, the counter is reloaded from the timer/event counter preload register and issues the interrupt request just like the other two modes. to enable the counting operation, the timer on bit (ton; bit 4 of tmrc) should be set to 1. in the pulse width measurement mode, the ton will be cleared au - tomatically after the measurement cycle is completed. but in the other two modes the ton can only be reset by instructions. the overflow of the timer/event counter is one of the wake-up sources. no matter what the opera- tion mode is, writin ga0toetican disable the interrupt service. HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 16 december 28, 2004 in the case of timer/event counter off condition, writing data to the timer/event counter preload register will also reload that data to the timer/event counter. but if the timer/event counter is turned on, data written to it will only be kept in the timer/event counter preload register. the timer/event counter will still operate until overflow occurs. when the timer/event counter (reading tmr) is read, the clock will be blocked to avoid errors. as clock blocking may results in a counting error, this must be taken into consideration by the programmer. the bit0~bit2 of the tmrc can be used to define the pre-scaling stages of the internal clock sources of timer/event counter. the definitions are as shown. the overflow signal of timer/event counter can be used to generate the pfd signal. input/output ports there are 13 bidirectional input/output lines in the microcontroller, labeled as pa, pb and pd, which are mapped to the data memory of [12h], [14h] and [18h] respectively. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, that is, the inputs must be ready at the t2 rising edge of instruction mov a,[m] (m=12h, 14h or 18h). for output operation, all the data is latched and remains unchanged until the output latch is rewritten. each i/o line has its own control register (pac, pbc, pdc) to control the input/output configuration. with this control register, cmos output or schmitt trigger input with or without pull-high resistor structures can be re - configured dynamically (i.e. on-the-fly) under software control. to function as an input, the corresponding latch of the control register must write 1 . the input source also depends on the control register. if the control regis- ter bit is 1 , the input will read the pad state. if the con- trol register bit is 0 , the contents of the latches will move to the internal bus. the latter is possible in the read-modify-write instruction. - 9 , : + = 2 ! ) 0 $ ) 0 $ $ % + = 2 9 0 $ : & ! % , - 9 1 + : f # f f # f 0 ! % + ! 0 ! % ( ! % & 0 ! % + ! ! % ! 1 4 , - 5 . 6 1 1 4 , , 1 + input/output ports 1 1 0 % + ! & ( % & 0 7 2 ! ! 3 0 & ! % 7 2 ! ! 3 % 0 & 3 ) 0 a - 7 2 % % " 0 7 2 ) / ) 4 1 9 5 < : + 1 ! " ! timer/event counter HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 17 december 28, 2004 for output function, cmos is the only configuration. these control registers are mapped to locations 13h, 15h and 19h. after a chip reset, these input/output lines remain at high levels or floating state (dependent on pull-high options). each bit of these input/output latches can be set or cleared by set [m].i and clr [m].i (m=12h, 14h or 18h) instructions. some instructions first input data and then follow the output operations. for example, set [m].i , clr [m].i , cpl [m] , cpla [m] read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. each line of port a has the capability of waking-up the device. the highest 4-bit of port b and 7 bits of port d are not physically implemented; on reading them a 0 is returned whereas writing then results in a no-operation. see application note. each i/o line has a pull-high option. once the pull-high option is selected, the i/o line has a pull-high resistor, otherwise, there s none. take note that a non-pull-high i/o line operating in input mode will cause a floating state. the pa3 is pin-shared with the pfd signal. if the pfd option is selected, the output signal in output mode of pa3 will be the pfd signal generated by the timer/event counter overflow signal. the input mode always remain- ing its original functions. once the pfd option is se- lected, the pfd output signal is controlled by pa3 data register only. writing 1 to pa3 data register will enable the pfd output function and writing 0 will force the pa3 to remain at 0 . the i/o functions of pa3 are shown below. i/o mode i/p (normal) o/p (normal) i/p (pfd) o/p (pfd) pa3 logical input logical output logical input pfd (timer on) note: the pfd frequency is the timer/event counter overflow frequency divided by 2. the pa5 and pa4 are pin-shared with int and tmr pins respectively. the pb can also be used as a/d converter inputs. the a/d function will be described later. there is a pwm function shared with pd0. if the pwm function is en - abled, the pwm signal will appear on pd0 (if pd0 is op - erating in output mode). writing 1 to pd0 data register will enable the pwm output function and writing 0 will force the pd0 to remain at 0 . the i/o functions of pd0 are as shown. i/o mode i/p (normal) o/p (normal) i/p (pwm) o/p (pwm) pd0 logical input logical output logical input pwm it is recommended that unused or not bonded out i/o lines should be set as output pins by software instruction to avoid consuming power under input floating state. pwm the microcontroller provides 1 channel (6+2) bits pwm output shared with pd0. the pwm channel has its data register denoted as pwm (1ah). the frequency source of the pwm counter comes from f sys . the pwm register is an eight bits register. the waveforms of pwm output are as shown. once the pd0 is selected as the pwm output and the output function of pd0 is enabled (pdc.0= 0 ), writing 1 to pd0 data register will enable the pwm output function and writing 0 will force the pd0 to stay at 0 . a pwm cycle is divided into four modulation cycles (modulation cycle 0~modulation cycle 3). each modula - tion cycle has 64 pwm input clock period. in a (6+2) bit pwm function, the contents of the pwm register is di- vided into two groups. group 1 of the pwm register is denoted by dc which is the value of pwm.7~pwm.2. the group 2 is denoted by ac which is the value of pwm.1~pwm.0. in a pwm cycle, the duty cycle of each modulation cycle is shown in the table. parameter ac (0~3) duty cycle modulation cycle i (i=0~3) i HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 19 december 28, 2004 bit no. label function 0 1 2 acs0 acs1 acs2 acs2, acs1, acs0: select a/d channel 0, 0, 0: an0 0, 0, 1: an1 0, 1, 0: an2 0, 1, 1: an3 1, x, x: undefined, cannot be used 3 4 5 pcr0 pcr1 pcr2 pcr2, pcr1, pcr0: pb3~pb0 configurations 0, 0, 0: pb3 pb2 pb1 pb0 (the adc circuit is power off to reduce power consumption.) 0, 0, 1: pb3 pb2 pb1 an0 0, 1, 0: pb3 pb2 an1 an0 0, 1, 1: pb3 an2 an1 an0 1, x, x: an3 an2 an1 an0 6 eocb end of a/d conversion flag. (0: end of a/d conversion) 7 start start the a/d conversion 0 1 0= start 0 1= reset a/d converter and set eocb to 1 adcr (22h) register bit no. label function 0 1 adcs0 adcs1 select the a/d converter clock source. 0, 0: f sys /2 0, 1: f sys /8 1, 0: f sys /32 1, 1: undefined, cannot be used. 2~6 unused bit, read as 0 . 7 test for internal test only. acsr (23h) register " 3 % ! ! " 3 % ! ! 1 1 1 1 1 1 1 1 1 1 1 1 1 4 1 4 1 a 2 % & ) " 3 % ! b ) ! " ) ! ! b 0 " 0 " ( 0 d % % % d " 3 ! % a & ) ) & " a " % ! " 0 " = % > ) / . ) / 7 ) / , i 5 ) ? 5 5 ? 5 5 i 6 5 ) ? 5 6 ? 5 6 i , ) ? 5 5 ? 5 5 i , ) ? 5 6 ? 5 6 b ) " 3 % ! % " 3 1 1 1 1 1 ) " 3 % ! % " 3 % 0 ! ! ! ! ! % " ! " $ " 0 & & & j " 0 ! ! & ) " 3 % ! a/d conversion timing HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 20 december 28, 2004 the following two programming examples illustrate how to setup and implement an a/d conversion. in the first exam - ple, the method of polling the eocb bit in the adcr register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. example: using eocb polling method to detect end of conversion clr intc.3 ; disable a/d interrupt in interrupt control register mov a,00100000b mov adcr,a ; setup adcr register to configure port pb0~pb3 as a/d inputs and select ; an0 to be connected to the a/d converter mov a,00000001b mov acsr,a ; setup the acsr register to select f sys /8 as the a/d clock start_conversion: clr adcr.7 set adcr.7 ; reset a/d clr adcr.7 ; start a/d polling_eoc: sz adcr.6 ; poll the adcr register eocb bit to detect end of a/d conversion jmp polling_eoc ; continue polling mov a,adr ; read conversion result from the adr (HT46R46/ht46c46) or ; adrh, adrl (ht46r47/ht46c47) register mov adr_buffer,a ; save result to user defined register : : jmp start_conversion ; start next a/d conversion example: using interrupt method to detect end of conversion set intc.0 ; interrupt global enable set intc.3 ; enable a/d interrupt in interrupt control register mov a,00100000b mov adcr,a ; setup adcr register to configure port pb0~pb3 as a/d inputs and select ; an0 to be connected to the a/d converter mov a,00000001b mov acsr,a ; setup the acsr register to select f sys /8 as the a/d clock start_conversion: clr adcr.7 set adcr.7 ; reset a/d clr adcr.7 ; start a/d : : ; interrupt service routine eoc_service routine: mov a_buffer,a ; save acc to user defined register mov a,adr ; read conversion result from the adr (HT46R46/ht46c46) or ; adrh, adrl (ht46r47/ht46c47) register mov adr_buffer,a ; save result to user defined register clr adcr.7 set adcr.7 ; reset a/d clr adcr.7 ; start a/d mov a,a_buffer ; restore acc from temporary storage reti HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 21 december 28, 2004 low voltage reset lvr the microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. if the supply voltage of the device is within the range 0.9v~3.3v, such as changing a battery, the lvr will au - tomatically reset the device internally. the lvr includes the following specifications: the low voltage (0.9v~v lvr ) has to remain in their original state to exceed 1ms. if the low voltage state does not exceed 1ms, the lvr will ignore it and do not perform a reset function. the lvr uses the or function with the external res signal to perform chip reset. the relationship between v dd and v lvr is shown below. note: v opr is the voltage range for proper chip operation at 4mhz system clock. d , d 1 d 1 d 8 ' d d ' 1 d 8 1 % ! 0 % e e 0 ! % ' " 0 low voltage reset note: *1: to make sure that the system oscillator has stabilized, the sst provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: since the low voltage has to maintain in its original state and exceed 1ms, therefore 1ms delay enter the reset mode. options the following table shows all kinds of options in the microcontroller. all of the options must be defined to ensure proper system functioning. no. options 1 wdt clock source: wdtosc or t1 (f sys /4) 2 wdt function: enable or disable 3 clrwdt instruction(s): one or two clear wdt instruction(s) 4 system oscillator: rc or crystal 5 pull-high resistors (pa, pb, pd): none or pull-high 6 pwm enable or disable 7 pa0~pa7 wake-up: enable or disable 8 pfd enable or disable 9 low voltage reset selection: enable or disable lvr function. application circuits the following table shows the c1, c2 and r1 values corresponding to the different crystal values. (for reference only) crystal or resonator c1, c2 r1 4mhz crystal 0pf 10k 4mhz resonator 10pf 12k 3.58mhz crystal 0pf 10k 3.58mhz resonator 25pf 10k 2mhz crystal & resonator 25pf 10k 1mhz crystal 35pf 27k 480khz resonator 300pf 9.1k 455khz resonator 300pf 10k 429khz resonator 300pf 10k the function of the resistor r1 is to ensure that the oscillator will switch off should low voltage condi - tions occur. such a low voltage, as mentioned here, is one which is less than the lowest value of the mcu operating voltage. note however that if the lvr is enabled then r1 can be removed. note: the resistance and capacitance for reset circuit should be designed in such a way as to ensure that the vdd is stable and remains within a valid operating voltage range before bringing res to high. * make the length of the wiring, which is connected to the res pin as short as possible, to avoid noise interference. HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 22 december 28, 2004 ! " ! 1 d - e 1 1 = 1 d - 1 d 1 - e 1 = , 1 = k k 6 1 = ) / 6 1 - - ( 3 0 % . % > 0 > 0 a ! 1 + 4 1 1 , , 1 4 , - 5 4 6 instruction set summary mnemonic description instruction cycle flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry and result in data memory decimal adjust acc for addition with result in data memory 1 1 (1) 1 1 1 (1) 1 1 1 (1) 1 1 (1) 1 (1) z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] and data memory to acc or data memory to acc exclusive-or data memory to acc and acc to data memory or acc to data memory exclusive-or acc to data memory and immediate data to acc or immediate data to acc exclusive-or immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 (1) 1 (1) 1 (1) 1 1 1 1 (1) 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 (1) 1 1 (1) z z z z rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 (1) 1 1 (1) 1 1 (1) 1 1 (1) none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 (1) 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 (1) 1 (1) none none HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 23 december 28, 2004 mnemonic description instruction cycle flag affected branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 (2) 1 (2) 1 (2) 1 (2) 1 (3) 1 (3) 1 (2) 1 (2) 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read rom code (current page) to data memory and tblh read rom code (last page) to data memory and tblh 2 (1) 2 (1) none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 (1) 1 (1) 1 1 1 1 (1) 1 1 none none none to,pdf to (4) ,pdf (4) to (4) ,pdf (4) none none to,pdf note: x: immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address : flag is affected : flag is not affected (1) : if a loading to the pcl register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). (2) : if a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). otherwise the original instruction cycle is unchanged. (3) : (1) and (2) (4) : the flags may be affected by the execution status. if the watchdog timer is cleared by executing the clr wdt1 or clr wdt2 instruction, the to and pdf are cleared. otherwise the to and pdf flags remain unchanged. HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 24 december 28, 2004 instruction definition adc a,[m] add data memory and carry to the accumulator description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the accumulator. operation acc acc+[m]+c affected flag(s) to pdf ov z ac c adcm a,[m] add the accumulator and carry to data memory description the contents of the specified data memory, accumulator and the carry flag are added si - multaneously, leaving the result in the specified data memory. operation [m] acc+[m]+c affected flag(s) to pdf ov z ac c add a,[m] add data memory to the accumulator description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc+[m] affected flag(s) to pdf ov z ac c add a,x add immediate data to the accumulator description the contents of the accumulator and the specified data are added, leaving the result in the accumulator. operation acc acc+x affected flag(s) to pdf ov z ac c addm a,[m] add the accumulator to the data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the data memory. operation [m] acc+[m] affected flag(s) to pdf ov z ac c HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 25 december 28, 2004 and a,[m] logical and accumulator with data memory description data in the accumulator and the specified data memory perform a bitwise logical_and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) to pdf ov z ac c and a,x logical and immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) to pdf ov z ac c andm a,[m] logical and data memory with the accumulator description data in the specified data memory and the accumulator perform a bitwise logical_and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) to pdf ov z ac c call addr subroutine call description the instruction unconditionally calls a subroutine located at the indicated address. the program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. the indicated address is then loaded. program execution continues with the instruction at this address. operation stack program counter+1 program counter addr affected flag(s) to pdf ov z ac c clr [m] clear data memory description the contents of the specified data memory are cleared to 0. operation [m] 00h affected flag(s) to pdf ov z ac c HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 26 december 28, 2004 clr [m].i clear bit of data memory description the bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) to pdf ov z ac c clr wdt clear watchdog timer description the wdt is cleared (clears the wdt). the power down bit (pdf) and time-out bit (to) are cleared. operation wdt 00h pdf and to 0 affected flag(s) to pdf ov z ac c 00 clr wdt1 preclear watchdog timer description together with clr wdt2, clears the wdt. pdf and to are also cleared. only execution of this instruction without the other preclear instruction just sets the indicated flag which im - plies this instruction has been executed and the to and pdf flags remain unchanged. operation wdt 00h* pdf and to 0* affected flag(s) to pdf ov z ac c 0* 0* clr wdt2 preclear watchdog timer description together with clr wdt1, clears the wdt. pdf and to are also cleared. only execution of this instruction without the other preclear instruction, sets the indicated flag which im- plies this instruction has been executed and the to and pdf flags remain unchanged. operation wdt 00h* pdf and to 0* affected flag(s) to pdf ov z ac c 0* 0* cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously containe d a 1 are changed to 0 and vice-versa. operation [m] [m ] affected flag(s) to pdf ov z ac c HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 27 december 28, 2004 cpla [m] complement data memory and place result in the accumulator description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice-versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m ] affected flag(s) to pdf ov z ac c daa [m] decimal-adjust accumulator for addition description the accumulator value is adjusted to the bcd (binary coded decimal) code. the accumu - lator is divided into two nibbles. each nibble is adjusted to the bcd code and an internal carry (ac1) will be done if the low nibble of the accumulator is greater than 9. the bcd ad - justment is done by adding 6 to the original value if the original value is greater than 9 or a carry (ac or c) is set; otherwise the original value remains unchanged. the result is stored in the data memory and only the carry flag (c) may be affected. operation if acc.3~acc.0 >9 or ac=1 then [m].3~[m].0 (acc.3~acc.0)+6, ac1=ac else [m].3~[m].0 (acc.3~acc.0), ac1=0 and if acc.7~acc.4+ac1 >9 or c=1 then [m].7~[m].4 acc.7~acc.4+6+ac1,c=1 else [m].7~[m].4 acc.7~acc.4+ac1,c=c affected flag(s) to pdf ov z ac c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) to pdf ov z ac c deca [m] decrement data memory and place result in the accumulator description data in the specified data memory is decremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) to pdf ov z ac c HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 28 december 28, 2004 halt enter power down mode description this instruction stops program execution and turns off the system clock. the contents of the ram and registers are retained. the wdt and prescaler are cleared. the power down bit (pdf) is set and the wdt time-out bit (to) is cleared. operation program counter program counter+1 pdf 1 to 0 affected flag(s) to pdf ov z ac c 01 inc [m] increment data memory description data in the specified data memory is incremented by 1 operation [m] [m]+1 affected flag(s) to pdf ov z ac c inca [m] increment data memory and place result in the accumulator description data in the specified data memory is incremented by 1, leaving the result in the accumula - tor. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) to pdf ov z ac c jmp addr directly jump description the program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. operation program counter addr affected flag(s) to pdf ov z ac c mov a,[m] move data memory to the accumulator description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) to pdf ov z ac c HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 29 december 28, 2004 mov a,x move immediate data to the accumulator description the 8-bit data specified by the code is loaded into the accumulator. operation acc x affected flag(s) to pdf ov z ac c mov [m],a move the accumulator to data memory description the contents of the accumulator are copied to the specified data memory (one of the data memories). operation [m] acc affected flag(s) to pdf ov z ac c nop no operation description no operation is performed. execution continues with the next instruction. operation program counter program counter+1 affected flag(s) to pdf ov z ac c or a,[m] logical or accumulator with data memory description data in the accumulator and the specified data memory (one of the data memories) per- form a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) to pdf ov z ac c or a,x logical or immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or x affected flag(s) to pdf ov z ac c orm a,[m] logical or data memory with the accumulator description data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_or operation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) to pdf ov z ac c HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 30 december 28, 2004 ret return from subroutine description the program counter is restored from the stack. this is a 2-cycle instruction. operation program counter stack affected flag(s) to pdf ov z ac c ret a,x return and place immediate data in the accumulator description the program counter is restored from the stack and the accumulator loaded with the speci - fied 8-bit immediate data. operation program counter stack acc x affected flag(s) to pdf ov z ac c reti return from interrupt description the program counter is restored from the stack, and interrupts are enabled by setting the emi bit. emi is the enable master (global) interrupt bit. operation program counter stack emi 1 affected flag(s) to pdf ov z ac c rl [m] rotate data memory left description the contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7 affected flag(s) to pdf ov z ac c rla [m] rotate data memory left and place result in the accumulator description data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 [m].7 affected flag(s) to pdf ov z ac c HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 31 december 28, 2004 rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated 1 bit left. bit 7 re - places the carry bit; the original carry flag is rotated into the bit 0 position. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 c c [m].7 affected flag(s) to pdf ov z ac c rlca [m] rotate left through carry and place result in the accumulator description data in the specified data memory and the carry flag are rotated 1 bit left. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. the rotated result is stored in the accumulator but the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) acc.0 c c [m].7 affected flag(s) to pdf ov z ac c rr [m] rotate data memory right description the contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0 affected flag(s) to pdf ov z ac c rra [m] rotate right and place result in the accumulator description data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 [m].0 affected flag(s) to pdf ov z ac c rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are together rotated 1 bit right. bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 c c [m].0 affected flag(s) to pdf ov z ac c HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 32 december 28, 2004 rrca [m] rotate right through carry and place result in the accumulator description data of the specified data memory and the carry flag are rotated 1 bit right. bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. the rotated result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) acc.7 c c [m].0 affected flag(s) to pdf ov z ac c sbc a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the accumulator. operation acc acc+[m ]+c affected flag(s) to pdf ov z ac c sbcm a,[m] subtract data memory and carry from the accumulator description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+c affected flag(s) to pdf ov z ac c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, [m] ([m] 1) affected flag(s) to pdf ov z ac c sdza [m] decrement data memory and place result in acc, skip if 0 description the contents of the specified data memory are decremented by 1. if the result is 0, the next instruction is skipped. the result is stored in the accumulator but the data memory remains unchanged. if the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy - cles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m] 1)=0, acc ([m] 1) affected flag(s) to pdf ov z ac c HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 33 december 28, 2004 set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) to pdf ov z ac c set [m]. i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) to pdf ov z ac c siz [m] skip if increment data memory is 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the fol - lowing instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, [m] ([m]+1) affected flag(s) to pdf ov z ac c siza [m] increment data memory and place result in acc, skip if 0 description the contents of the specified data memory are incremented by 1. if the result is 0, the next instruction is skipped and the result is stored in the accumulator. the data memory re- mains unchanged. if the result is 0, the following instruction, fetched during the current in- struction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if ([m]+1)=0, acc ([m]+1) affected flag(s) to pdf ov z ac c snz [m].i skip if bit i of the data memory is not 0 description if bit i of the specified data memory is not 0, the next instruction is skipped. if bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). other - wise proceed with the next instruction (1 cycle). operation skip if [m].i 0 affected flag(s) to pdf ov z ac c HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 34 december 28, 2004 sub a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. operation acc acc+[m ]+1 affected flag(s) to pdf ov z ac c subm a,[m] subtract data memory from the accumulator description the specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+1 affected flag(s) to pdf ov z ac c sub a,x subtract immediate data from the accumulator description the immediate data specified by the code is subtracted from the contents of the accumula - tor, leaving the result in the accumulator. operation acc acc+x +1 affected flag(s) to pdf ov z ac c swap [m] swap nibbles within the data memory description the low-order and high-order nibbles of the specified data memory (1 of the data memo- ries) are interchanged. operation [m].3~[m].0 [m].7~[m].4 affected flag(s) to pdf ov z ac c swapa [m] swap data memory and place result in the accumulator description the low-order and high-order nibbles of the specified data memory are interchanged, writ - ing the result to the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0 [m].7~[m].4 acc.7~acc.4 [m].3~[m].0 affected flag(s) to pdf ov z ac c HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 35 december 28, 2004 sz [m] skip if data memory is 0 description if the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) to pdf ov z ac c sza [m] move data memory to acc, skip if 0 description the contents of the specified data memory are copied to the accumulator. if the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m]=0 affected flag(s) to pdf ov z ac c sz [m].i skip if bit i of the data memory is 0 description if bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc - tion (2 cycles). otherwise proceed with the next instruction (1 cycle). operation skip if [m].i=0 affected flag(s) to pdf ov z ac c tabrdc [m] move the rom code (current page) to tblh and data memory description the low byte of rom code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh rom code (high byte) affected flag(s) to pdf ov z ac c tabrdl [m] move the rom code (last page) to tblh and data memory description the low byte of rom code (last page) addressed by the table pointer (tblp) is moved to the data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh rom code (high byte) affected flag(s) to pdf ov z ac c HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 36 december 28, 2004 xor a,[m] logical xor accumulator with data memory description data in the accumulator and the indicated data memory perform a bitwise logical exclu - sive_or operation and the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) to pdf ov z ac c xorm a,[m] logical xor data memory with the accumulator description data in the indicated data memory and the accumulator perform a bitwise logical exclu - sive_or operation. the result is stored in the data memory. the 0 flag is affected. operation [m] acc xor [m] affected flag(s) to pdf ov z ac c xor a,x logical xor immediate data to the accumulator description data in the accumulator and the specified data perform a bitwise logical exclusive_or op - eration. the result is stored in the accumulator. the 0 flag is affected. operation acc acc xor x affected flag(s) to pdf ov z ac c HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 37 december 28, 2004 package information 18-pin dip (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 895 915 b 240 260 c 125 135 d 125 145 e16 20 f50 70 g 100 h 295 315 i 335 375 0 15 HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 38 december 28, 2004 7 1 8 - * ? 18-pin sop (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 394 419 b 290 300 c14 20 c 447 460 d92 104 e 50 f4 g32 38 h4 12 0 10 HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 39 december 28, 2004 7 1 8 - * ? j product tape and reel specifications reel dimensions sop 18w symbol description dimensions in mm a reel outer diameter 330 1.0 b reel inner diameter 62 1.5 c spindle hole diameter 13.0+0.5 0.2 d key slit width 2.0 0.5 t1 space between flange 24.8+0.3 0.2 t2 reel thickness 30.2 0.2 HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 40 december 28, 2004 carrier tape dimensions sop 18w symbol description dimensions in mm w carrier tape width 24.0+0.3 0.1 p cavity pitch 16.0 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 11.5 0.1 d perforation diameter 1.5 0.1 d1 cavity hole diameter 1.5+0.25 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 10.9 0.1 b0 cavity width 12.0 0.1 k0 cavity depth 2.8 0.1 t carrier tape thickness 0.3 0.05 c cover tape width 21.3 HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 41 december 28, 2004 + 1 - # 1 1 1 HT46R46/ht46c46/ht46r47/ht46c47 rev. 1.00 42 december 28, 2004 copyright 2004 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) 7th floor, building 2, no.889, yi shan rd., shanghai, china 200233 tel: 021-6485-5560 fax: 021-6485-0313 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 43f, seg plaza, shen nan zhong road, shenzhen, china 518031 tel: 0755-8346-5589 fax: 0755-8346-5590 isdn: 0755-8346-5591 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 010-6641-0030, 6641-7751, 6641-7752 fax: 010-6641-0125 holmate semiconductor, inc. (north america sales office) 46712 fremont blvd., fremont, ca 94538 tel: 510-252-9880 fax: 510-252-9885 http://www.holmate.com |
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